Data processing system



June 7, 1966 L O D ETAL 3,255,438

DATA PROCESSING SYSTEM INS l FWD DTI L l \J LJ L| 0T3 F U lf Tf LF Z U Eggs INS FWD U U LF LT U l j- AEI EIS F/GTZA U INS U LF U EIS TE l V REV T U TFR T EIP T F LP June 7, 1966 Filed June L3, 1962 ACCELERATION TIME E. LEONARD ETAL 3,255,438

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E. LEONARD ETAL 3,255,438

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E. LEONARD ETAL DATA PROCESSING SYSTEM June 7, 1966 Filed June H5, 1962 mm? o .E H3

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DATA PROCESSING SYSTEM 64 Sheets-Sheet 19 FIELD DE FINITION AND SCAN CONTROL BOARD ABCDEFGHJKLMNPORSTUVWXYZ SECTION A F/G. I634 June 7, 1966 Filed June 13, 1962 E. LEONARD ETAL June 7, 1966 DATA PROCESSING SYSTEM 64 Sheets-Sheet 20 Filed June 13, 1962 FIELD DEFIN1T1ON uo o INHIBITHUBS O O O O O 0 9 0 I 0 0 0 0 0 0 O I O 0 0 0 O 0 0 0 0 0 0 0 0 0 O I O 0 0 0 O 0 0 I O I 0 0 0 01110 ARTS O O 0 0 0 6 O O 0 0 0 O 0 0 0 0 O I 0 0 UINII T non NIIIT s NLTION 0 6 C To U 0 Q I I 0 0 I 0 0 O DEFJNA u DEF-'1,

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1. IN A DATA PROCESSING SYSTEM, AT LEAST TWO CHARACTERADDRESSABLE MEMORY UNITS RESPONSIVE TO ADDRESSING AND TIMING SIGNALS FOR ACCEPTING AND DELIVERING DATA; A PRIMARY COUNTER COMMON TO ALL MEMORY UNITS, SAID PRIMARY COUNTER INCLUDING A STEPPING INPUT, A CLEARING INPUT, AND CIRCUITS FOR EMITTING FIELD SIGNALS CORRESPONDING TO AT LEAST ONE CONTIGUOUS SEQUENCE OF STABLE STATES OF SAID PRIMARY COUNTER AND A GROUP OF PRIMARY STATUS SIGNALS UNIQUELY INDICATIVE OF THE CURRENT STATE OF SAID PRIMARY COUNTER; A SECONDARY COUNTER ASSOCIATED WITH EACH MEMORY UNIT INCLUDING A STEPPING INPUT, A CLEARING INPUT, AND CIRCUITS FOR EMITTING A GROUP OF SECONDARY STATUS SIGNALS UNIQUELY INDICATIVE OF THE CURRENT STATE OF SAID SECONDARY COUNTER; CLEARING INPUTS OF SAID PRIMARY AND ALL OF SAID SECONDARY COUNTERS BEING MUTUALLY INDEPENDENT; AN ADDRESSING SIGNAL GENERATOR ASSOCIATED WITH EACH OF SAID MEMORY UNITS AND RESPONSIVE JOINTLY TO SAID GROUP OF PRIMARY STATUS SIGNALS AND TO THE GROUP OF SECONDARY STATUS SIGNALS OF THE SECONDARY COUNTER ASSOCIATED WITH SAID MEMORY UNIT; A PLURALITY OF SIMULTANEOUSLY OPERABLE DATA PROCESSING CIRCUITS RESPONSIVE TO SAID FIELD SIGNALS AND TO DATA SIGNALS FROM SAID MEMORY UNITS, CERTAIN OF SAID PROCESSING CIRCUITS INCLUDING FACILITIES OF INVERTING THE NORMAL SEQUENCE OF DATA TRANSFER; A PLURALITY OF TIMING SIGNAL GENERATORS, EACH ASSOCIATED WITH AT LEAST ONE OF SAID PROCESSING CIRCUITS; CERTAIN OF SAID MEMORY UNITS INCLUDING LOADING FACILITIES RESPONSIVE TO CERTAIN PREDETERMINED COMBINATIONS OF 